1. Field of the Invention
The present invention relates to a semiconductor memory device having a multi-bank, each bank having a plurality of local data buses connected to global data bus.
2. Description of the Related Art
FIG. 7 is a schematic block diagram showing a configuration of a prior art synchronous DRAM with banks 0 and 1 of the same architecture.
For example, when contents of memory cells C1 and C2 in a memory cell array 10 of the bank 0 are read out, a word line WL is activated by a row decoder 11, whereby a plurality of memory cells coupled to the word line WL are conducted to bit line pairs of respective columns and very small changes in voltage between the bit line pairs are amplified by sense amplifier rows 31 and 32 arranged at both sides of a memory cell block 21 including the word line WL.
On the other hand, block switches BS01 and BS02 corresponding to selected memory cell block 21 are switched on by a block decoder 13, thereby local data buses LDB01 and LDB02 routed in (above and along) the sense amplifier rows 31 and 32 are conducted to global data buses GDB1 and GDB0, respectively.
Then, a column selection line CSL is activated by a column decoder 12, thereby column switches CS20 to CS24 are switched on and voltages on bit lines connected to the column switches CS20 to CS24 are taken out onto local data buses LDB00 to LDB04. Since block switches BS00, BS03, BS04 and BS01 to BS14 are off except the block switches BS01 and BS02, voltages on the buses DB01 and LB02 are transmitted to the global data buses GDB1 and GDB0, then the voltages are amplified in a read/write amplifier 40, next the amplified voltages are converted to external voltages in an I/O data buffer 41 and taken out to the outside as DATA.
In a write operation, DATA provided from the exterior is converted into an internal voltage in the I/O data buffer 41, amplified in the read/write amplifier 40, and transmitted in a reverse direction to that in the read operation to write DATA into the selected memory cell.
Since a memory block is selected with an address in binary number, the number of the memory blocks is an even number "N", and the number of sense amplifier rows sandwiching memory blocks is an odd number (N +1). Further, since voltages are transmitted to different global data buses from local data buses routed in (above and along) sense amplifier rows sandwiching the selected block, the local data buses LDBOO to LDBO4 are alternately coupled to the global data buses GDB0 and GDB1.
Under such conditions, in the prior art, the same pattern has been repeated in laying out on a chip using the same pattern data for each bank to form a plurality of banks.
For this reason, the numbers of local data buses connected to the buses GBD0 and GBD1 are different from each other, and in a case of FIG. 7, the bus GBD0 has a heavier load than that of the bus GBD1. The operating speeds of read and write are determined by one of the buses whichever has a heavier load, which is a cause for slowing down the operating speed.